1. Field of the Invention
The present invention is related to nonvolatile storage and more particularly to integrated circuit chips including nonvolatile storage such as one or more or an array of nonvolatile random access memory (NVRAM) cells.
2. Background Description
Nonvolatile floating gate storage devices, such as may be used for memory cells in a nonvolatile random access memory (NVRAM), are well known in the industry. In such an NVRAM cell, the cell's conductive state is determined by the charge state of the storage device's floating gate. The floating gate is an electrically isolated gate of a field effect transistor (FET) stacked in a two device NAND-like structure. Charge is forced onto or removed from the floating gate through a thin insulator layer that, normally (during a read operation), isolates the gate electrically from other adjoining conductive layers. For example, a negatively (or positively) charged floating gate is representative of a binary one state, while an uncharged floating gate is representative of a binary zero state or, vice versa.
Typically, the other device in the NAND-like structure is connected to a word line and a bit line. In typical state of the art designs, adjacent cells are connected to a common bit line. The word lines of these adjacent cells must be uniquely addressable and physically distinct. Intersection of each word line with each bit line provides unique cell selection for reading and writing the selected cell. For reading, a read voltage (e.g., Vhi or ground) is applied to a control gate (or program gate) that is capacitively coupled to floating gates of the nonvolatile devices of devices being read. Thus, when the word line is raised, those devices programmed for zeros and those programmed for ones do not. For writing, a write voltage is applied to the control gate (or program gate) is capacitively coupled to floating gates of the nonvolatile devices and, when the gate, source and drain voltages are biased properly, the charge changes on the floating gate, i.e., to write selected cells.
Normally, once a state of the art device has been programmed, i.e., charge is forced on the floating gate, the device is first erased before it is re-written. While programming such a state of the art device using channel hot electron techniques may require voltages up to 5V, common erase operations using Fowler-Nordheim tunneling techniques that requires at least twice the write voltage. Thus, these nonvolatile storage devices require special decoder circuits and additional process complexity to handle much higher than normal erase voltages. Additional processing decreases yield. Lower yield increases per chip manufacturing cost. Consequently, the associated yield degradation and additional cost have always been a major inhibitor for embedding reprogrammable nonvolatile storage on other types of chips, e.g., dynamic RAM (DRAM), static RAM (SRAM), microprocessors, custom logic and etc.
Occasionally, logic applications may require some facility to reconfigure in situ or on the fly. Further, this reconfiguration may be infrequent, occurring only a few times over the life of the logic chip. Nonvolatile storage devices have been used for these applications with some success. However, the overhead and cost of including such a nonvolatile facility (e.g., circuit area added for decoders, high voltage drivers and additional processing to handle erase voltages) may outweigh the convenience of including it. This is especially true when scattering the nonvolatile devices across a chip may be most their efficiently use and/or when only a small amount of resident nonvolatile storage (e.g., several hundred, several thousand or even a million devices) is needed/desired. For example, the increase in memory chip cost for including nonvolatile redundancy selection may well outweigh the benefits of electrical programmability and make the memory chip unmarketable.
Thus, there is a need for nonvolatile storage devices that can be written/erased at voltage levels that are on the order of normal read voltages and that do not require special area consuming decode, erase and write circuits.